1. Field of the Invention
This invention relates to complimentary metal oxide semiconductor (CMOS) circuit designs, and more particularly, to multiplexer designs.
2. Description of the Related Art
In CMOS designs, traditional static CMOS multiplexer functions may typically be implemented using two or more stages of logic (e.g. a complex gate such as an and/or function). Each stage represents a gate delay to the input data. This means that the traditional static CMOS multiplexer may be slow. This may be especially true for multiple input multiplexers.
To reduce the gate delay and slow response of some static CMOS multiplexers, it is common to use pre-charge logic to implement wide fan-in bus drivers or other large multiplexer functions. Pre-charge logic is typically used to charge an output node to a binary one, and then if the output data is a binary zero, evaluating logic pulls the output node low. The pre-charging circuitry reduces the need for multiple logic stages used in static CMOS designs. Thus pre-charging may allow for a faster output response time. However, some CMOS multiplexer designs may require a large P-Channel load device per stage, which may have a large capacitance associated with it. Additionally, in cases where pre-charge logic may not be used such as, for example, when there is no clock available or the data is not synchronous to one of the clock edges, then a static CMOS multiplexer may be the only choice. Accordingly, it is desirable to have a faster multiple input static CMOS multiplexer design.